The 5th Workshop on
UnConventional High Performance Computing 2012 (UCHPC 2012)
August 27, Rhodes Island, Greece

held in conjunction with
Euro-Par 2012, August 27 - August 31, 2012
Rhodes Island, Greece

Topics
Program
Submission
Important Dates
Committees
Organizers

Call for Papers
in txt format

Previous UCHPC
Workshops:
2011 @ EuroPar'11
2010 @ EuroPar'10
2009 @ CF'09
2008 @ ICCSA'08


EuroPar 2012
Conference Home


News

Sep 24, 2012: Links to some slides added.

Background

As the word "UnConventional" in the title suggests, the workshop focuses on hardware and platforms for HPC, which were not intended for HPC in the first place. Reasons could be raw computing power, good performance per watt, or low cost in general. To address this unconventional hardware, often, new programming approaches and paradigms are required to make best use of it. Thus, a second focus of the workshop is on innovative new programming models for unconventional hardware and how to best combine its computing power with more conventional systems. To this end, UCHPC tries to capture solutions for HPC which are unconventional today but could become conventional and significant tomorrow.
For example, the computing power of platforms for games recently raised rapidly. This motivated the use of GPUs for computing (GPGPU), or even building computational grids from game consoles. The trend of integrating GPUs on processor chips seem to be very beneficial for use of both parts for HPC. Other examples for "unconventional" hardware are embedded, low-power processors, upcoming many-core architectures, FPGAs or DSPs. Thus, interesting devices for research in unconventional HPC are not only standard server or desktop systems, but also relative cheap devices due to being mass market products, such as smartphones, netbooks, tablets and small NAS servers. Especially smartphones seem to become more performance hungry every day. Only imagination sets the limit for use of the mentioned devices for HPC.

Topics

The goal of the workshop is to present latest research in how hardware and software (yet) unconventional for HPC is or can be used to reach goals such as best performance per watt. UCHPC also covers according programming models, compiler techniques, and tools. Thus, suggested topics for papers include, but are not limited to the following:
  • Innovative use of hardware and software unconventional for HPC
  • HPC applications or visualizations in connection with HPC on GPUs (GPGPU), using GPUs embedded on processor dies (as found in AMD Fusion/APUs, NVidia Denver, Intel Ivy Bridge), Intel's MIC and SCC, low power/embedded processors (including DSPs, Adapteva Epiphany), FPGAs (e.g. Convey), Tilera's tile-based many-core processors, IBM Cell BE, accelerators, visualization cards, etc.
  • Cluster/Grid solutions using unconventional hardware, e.g. clusters of game consoles, nodes using GPUs, Low Power/Embedded Processors, MPSoCs, new many-cores from Intel and/or ARM designs, Mac Minis/AppleTVs, FPGAs etc.
  • Heterogeneous computing on hybrid platforms
  • Work on and use of new programming models and paradigms needed to support unconventional hardware, and hybrid/hierarchical combinations with more conventional systems. Examples are OpenACC, OpenCL, Cilk+, and task-based approaches for heterogeneous systems
  • Performance and scalability studies in HPC using unconventional hardware
  • Reconfigurable Computing for HPC
  • Performance modeling, analysis and tools for HPC with unconventional hardware
  • New or adapted/extended (parallel) programming models for HPC with unconventional hardware


Program

The workshop takes place on Monday, 27th of August. It is scheduled as half-day in the morning.

Time  
9:30 Welcome and Introduction by Workshop Organizers
Josef Weidendorfer, Jan-Philipp Weiss
  Session 1
Chair: Jan-Philipp Weiss
 
9:35 Invited Talk 1
Programming Models for Next Generation HPC Systems (Slides)
Jens Breitbart
10:10 Methodology for Efficient Use of OpenCL, ESL and FPGAs in Multi-Core Architectures (Slides)
George Economakos
10:35 Spin glass simulations on the Janus architecture: a desperate quest for strong scaling (Slides)
M. Baity-Jesi, R.A. Banos, A. Cruz, L.A. Fernandez, J.M. Gil-Narvion, A. Gordillo-Guerrero, M. Guidetti, D. Iniguez, A. Maiorano, F. Mantovani, E. Marinari, V. Martin-Mayor, J. Monforte-Garcia, A. Munoz-Sudupe, D. Navarro, G. Parisi, S. Perez-Gaviro, M. Pivanti, F. Ricci-Tersenghi, J. Ruiz-Lorenzo, S.F. Schifano, B. Seoane, A. Tarancon, P. Tellez, R. Tripiccione, and D. Yllanes
11:00 Coffee Break
  Session 2
Chair: Josef Weidendorfer
11:30 Invited Talk 2
Is UCHPC the solution to the power challenge? (Slides)
Hartwig Anzt
12:05 Efficient Design Space Exploration of GPGPU Architectures (Slides)
Ali Jooya, Amirali Baniasadi, and Nikitas J. Dimopoulos
12:30 A CG-Solver for Future GPU Clusters Enhanced with Memory Accelerators
Noboru Tanabe, Junko Kogou, Sonoko Tomimori, Masami Takata and Kazuki Joe
12:55 Workshop Closing

Abstracts of invited talks

Jens Breitbart: Programming Models for Next Generation HPC Systems

Over the last decade supercomputers and processor designs became power constrained and performance per watt is slowly becoming the major limiting factor regarding absolute performance. However, increasing power efficiency is not a trivial task for current processor designs, as most power is consumed by memory accesses and data transfers, not by computation.
In this talk we discuss possible hardware changes and how they interfere with current programming models.

Hartwig Anzt: Is UCHPC the solution to the power challenge?

As we approach the Exascale computing era, the focus of the scientific computing community increasingly turns to energy efficiency hard- and software, able to tackle applications with low power consumption. The reasons are not only the running energy costs that often exceed the acquisition cost of a hardware platform after short time, but also the need for appropriate infrastructure and the concerns about an upcoming energy crisis and global warming.
Against this background, unconventional high performance computing may provide a valuable contribution on the road to Exascale. On the technical side, hardware developers aim at lowering the energy consumption e.g. by designing hybrid hardware platforms equipped with coprocessors like GPUs, FPGAs or Intel's MIC that can conduct operations with higher efficiency, or introducing techniques able to scale down the power demand. However, the hardware-driven approach to energy-efficient computing is not sufficient as many computing centers are nowadays equipped with hardware featuring energy-saving techniques, but most scientific applications are still oblivious to the power consumption. Significant reduction in the energy record can only be achieved if the full computing power is leveraged and the featured energy saving techniques are applied. This often requires not only the adaptation, but moreover the redesign of the algorithms and implementation. Hence, using unconventional hardware demands for unconventional methods also on the software side.
In this talk I will provide an example about how GPUs can efficiently be used to improve the power profile of an algorithm. Furthermore, I will show how replacing classical numerics by unconventional methods can be beneficial to the energy consumption of a scientific application.


Paper Submission, Registration, and Publication

Workshop papers can not exceed ten single-spaced, single-column pages (LNCS style). Submission implies that at least one author will register for the workshops at Euro-Par 2012 and present the paper in the workshop session, if accepted.

Upload your submission to our submission server in PDF format. It must not be simultaneously submitted to the main conference or any other publication outlet.

For the workshop, we will prepare handouts with the revised papers. These will be published after the conference in the workshop proceedings of Euro-Par 2012, part of the LNCS series of Springer.


Important Dates

June 11, 2012: Submission deadline (extended, was June 4)
July 6, 2012: Notification of acceptance
July 20, 2012: Camera ready, revised papers due
August 27-31, 2012: Conference with workshops


Committees

International Program Committee

David A. Bader, Georgia Tech, US
Michael Bader, Technische Universität München, DE
Denis Barthou, Universite de Bordeaux, FR
Lars Bengtsson, Chalmers University of Technology, SE
Giorgos Dimitrakopoulos, Democritus University of Thrace, GR
Karl Fürlinger, LMU, DE
Dominik Göddeke, TU Dortmund, DE
Georg Hager, University Erlangen-Nuremberg, DE
Anders Hast, Uppsala University, SE
Ben Juurlink, TU Berlin, DE
Rainer Keller, Hochschule für Technik, Stuttgart, DE
Gaurav Khanna, University of Massachusetts Dartmouth, US
Harald Köstler, University Erlangen-Nuremberg, DE
Manfred Mücke, University of Vienna, AT
Andy Nisbet, Manchester Metropolitan University, UK
Ioannis Papaefstathiou, Technical University of Crete, GR
Franz-Josef Pfreundt, Fraunhofer ITWM, DE
Bertil Schmidt, University Mainz, DE
Dimitrios Soudris, National Technical University of Athens, GR
Ioannis Sourdis, Chalmers University of Technology, SE
Thomas Steinke, Zuse Institute, Berlin, DE
Josef Weidendorfer, Technische Universität München, DE
Jan-Philipp Weiss, KIT, DE
Stephan Wong, Delft University of Technology, NL
Ren Wu, HP Labs, Palo Alto, US
Peter Zinterhof jun., University of Salzburg, AT
Yunquan Zhang, Chinese Academy of Sciences, Beijing, CN

UCHPC Steering Committee

Lars Bengtsson, Chalmers University of Technology, SE
Anders Hast, Uppsala University, SE
Josef Weidendorfer, Technische Universität München, DE
Jan-Philipp Weiss, KIT, DE
Ren Wu, HP Labs, Palo Alto, US


UCHPC'12 Workshop Organizers

Anders Hast, Uppsala University, SE
Josef Weidendorfer, Technische Universität München, DE
Jan-Philipp Weiss, KIT, DE