Third Workshop on
UnConventional High Performance Computing 2010 (UCHPC 2010)
August 30st, Ischia - Naples, Italy

held in conjunction with
Euro-Par 2010, August 30st - September 3rd, 2010
Ischia - Naples, Italy, Hotel Continental Terme

Pictures New! Submission
Important Dates
PC Members

Call for Papers
in txt format

Previous UCHPC
2009 @ CF'09
2008 @ ICCSA'08

EuroPar 2010
Conference Home


The slides for the talks are now available. See the program section below.

Due to several requests, we have extended the submission deadline by one week. The new deadline is June 21th, 2010.


As the computing power of various platforms intended for games is increasing rapidly, they attract the interest of professionals in the HPC community. As an example, the modern graphics processing units (GPU) are often used for HPC in the so called field "General-Purpose computing on GPU's" (GPGPU). Another example is the Playstation3 (PS3) that has a multicore architecture that lends itself for HPC. These platforms are not conventional HPC platforms, nonetheless they are used for HPC purposes and even clusters of such computing resources are being built with great success. Both the raw computing power and the relatively low cost compared to conventional HPC resources make them very interesting. The aim of this workshop is to focus on such unconventional resources for HPC. Only imagination sets the limit for what this kind of devices can be used for in HPC, also by forming clusters.

The word "UnConventional" in the workshop title emphasizes that the focus is on hardware or platforms used for HPC, which were not intended for HPC in the first place. So, in some sense we try to capture things in this workshop that are being done in an unconventional way today but perhaps will be conventional tomorrow. That is why the C in UnConventional is in capital letters.


The goal of the session is to present latest research in how hardware and software (yet) unconventional for HPC is/can be used to reach given goals such as best performance/watt, with according programming models, compiler techniques and tools. Thus, suggested topics for papers include, but are not limited to the following:
  • Innovative use of hardware and software unconventional for HPC
  • HPC applications or visualizations in connection with HPC on GPUs (GPGPU), IBM Cell, Low Power Processors, FPGAs, Visualization cards etc.
  • Cluster/Grid solutions using unconventional hardware, e.g. clusters of PS3s, GPUs, Low Power Processors, MPSoCs, Mac Minis, FPGAs etc.
  • Performance and scalability studies in HPC using unconventional hardware
  • Reconfigurable Computing for HPC
  • Performance modeling, analysis and tools for HPC with unconventional hardware
  • New or adapted/extended (parallel) programming models for HPC with unconventional hardware


Date: Monday, 30th August

14:30 Welcome from the organizers (A. Hast, J. Weidendorfer)
  Session 1: Accelerator Usage for Applications  
14:40 Danilo De Donno, Alessandra Esposito, Giuseppina Monti, Luciano Tarricone:
"Iterative solution of linear systems in electromagnetics (and not only): Experiences with CUDA" (Slides)
15:00 Peter Zinterhof:
"Distributed Computation of Feature-Detectors for Medical Image Processing on GPGPU and Cell Processors" (Slides)
15:20 Liu Peng, Guangming Tan, Rajiv K. Kalia, Aiichiro Nakano, Priya Vashishta, Dongrui Fan, Ninghui Sun:
"Preliminary Investigation of Optimizing Molecular Dynamics Simulation on Godson-T Many-core Processor" (Slides)
15:40 Giorgio Gemignani, Lucia Maddalena, Alfredo Petrosino:
"Real-time Stopped Object Detection by Neural Dual Background Modeling" (Slides)
16:00 Coffee break
  Session 2: Accelerator Usage Infrastructure  
16:30 Jeff A. Stuart, Michael Cox, John D. Owens:
"GPU-to-CPU Callbacks" (Slides)
16:50 Jens Breitbart:
"Static GPU workgroups and an improved scan Algorithm" (Slides)
  Session 3: Speeding up Algorithms with Accelerators  
17:10 Jacobo Lobeiras Blanco:
"Streaming-Oriented Parallelization of Domain-Independent Irregular Kernels" (Slides)
17:30 Vincent Heuveline, Dimitar Lukarski, Jan-Philipp Weiss:
"Scalable Multi-Coloring Preconditioning for Multi-core CPUs and GPUs" (Slides)
17:50 Bernd Lesser, Manfred Mücke, Wilfried N. Gansterer:
"Peak Performance Model for a Custom Precision Floating-Point Dot Product on FPGAs" (Slides)
18:10 Workshop Closing


Paper Submission, Registration, and Publication

Workshop papers should not exceed eight single-spaced, single-column pages. As this is a workshop on a fast evolving topic, we encourage you to enhance your contribution with newest measurements even after the acceptance decision, but keep the total page limit in mind. Submission implies that at least one author will register for the workshops at Euro-Par 2010 and present the paper in the workshop session, if accepted.

Submissions should be sent to Anders Hast in PDF format, and must not be simultaneously submitted to the main conference or any other publication outlet.

For the workshop, we will prepare handouts with the final papers. These also will be published after the conference in the workshop proceedings of Euro-Par 2010, part of the LNCS series of Springer.

Important Dates

June 21th: Extended Submission deadline
July 19th: Notification of acceptance
Aug 23th: Final papers due
Aug 31th - Sep 3rd: Conference with workshops
Oct 2nd: Final review comments
Oct 16th: Camera ready papers

International Program Committee

Michael Bader, Universität Stuttgart, DE
Lars Bengtsson, Chalmers, SE
Duncan A. Buell, University of South Carolina, US
Karl Fürlinger, UC Berkeley, US
Dominik Göddeke, TU Dortmund, DE
Anders Hast, University of Gävle, SE
Rainer Keller, ORNL, US
Gaurav Khanna, University of Massachusetts Dartmouth, US
Dominique Lavenier, INRIA, FR
Malcolm Low Yoke Hean, Nanyang Technological University, SG
Ingela Nyström, UPPMAX, SE
Douglas Leslie Maskell, Nanyang Technological University, SG
Ioannis Papaefstathiou, Technical University of Crete, GR
Art Sedighi, Softmodule
Bertil Schmidt, Nanyang Technological University, SG
Carsten Trinitis, Technische Universität München, DE
Josef Weidendorfer, Technische Universität München, DE
Jan-Phillipp Weiss, KIT, DE
Ren Wu, HP Labs, Palo Alto, US

Workshop Organizers

Anders Hast, University in Gävle, SE
Lars Bengtsson, Chalmers University, SE
Josef Weidendorfer, Technische Universität München, DE
Ren Wu, HP Labs, Palo Alto, US