Third Workshop
on Issues and Solutions for Memory Access
on Cache Architectures:
"Is the Memory fit for Manycore?"
(MAW'09)

at the
2009 International Conference on Computing Frontiers

Background

The issues behind the "memory wall" have existed for quite some time now, and a realistic solution is not yet available in nowadays processors. While the multicore approach will presumably fulfill the performance increase expected from Moore's Law in the near future, slow access to main memory will continue to remain an obstacle and have a significant impact on the performance of applications. Even if a fast path to off-chip memory was availabe, the optimal connection and hierarchical configuration of on-chip execution units and buffers remain an open question, especially for general-purpose hardware.

Especially with manycore architectures in mind, the potentially available hardware on a chip for memory access, such as multiple cache controllers, explicitly programmable prefetching units and on-chip buffers, has to be exploited by software in an efficient way. Is it sufficient to have memory access agents for a group of cores, to avoid congestion? Or should we concentrate on prefetch-friendly programming models, distributed memory on a chip, or message-passing?

The goal of the session is to present latest research in how to overcome the problem of slow memory access with regard to an increasing number of cores on a chip. This comprises both work on the theoretical and on the practical front, including hardware and software solutions, as well as supporting compiler techniques and simulation/analysis tools.

Topics

Suggested topics for papers include, but are not limited to, the following:

• Compiler techniques
• Cache simulation tools and studies
• Code optimization strategies
• Tools for performance and cache behavior analysis
• Adaptive cache architectures
• Application studies regarding cache behavior
• Optimization algorithms
• Prefetch techniques

Paper Submission, Registration, and Publication

In general, rules of paper submission of the 2009 International Conference on Computing Frontiers apply. See the conference site at www.computingfrontiers.org. However, workshop paper manuscripts should not exceed eight single-spaced, single-column pages with 10-point font (these are guidelines for the review process; for the final version the publisher will sent its own guidelines). Submission implies that at least one author will register for the main conference and present the paper in the workshop session, if accepted. Submissions must be made electronically as PDF file to the workshop organizers, and must not be simultaneously submitted to the main conference or any other publication outlet.

The papers will be included onto the regular conference proceedings CD, and published in the ACM digital library.

Please send your workshop paper manuscript to Josef.Weidendorfer@cs.tum.edu.

Important Dates

Submission of Papers: Extended to February 6 (was January 28, 2009)
Notification of Acceptance: February 18, 2009
Camera-Ready Papers: March 15, 2009
Conference: May 18 - 20, 2009

Session Organizers

Rainer Buchty, Universität Karlsruhe (TH), Germany
Jie Tao, Institute for Scientific Computing Karlsruhe, Germany
Josef Weidendorfer, Technische Universität München, Germany