Foto von Josef Weidendorfer

Dr. rer. nat. Josef Weidendorfer

Technische Universität München

Informatik 10 - Lehrstuhl für Rechnertechnik und Rechnerorganisation (Prof. Bode)

Postadresse

Postal:
Boltzmannstr. 3
85748 Garching b. München

Short CV

Josef Weidendorfer is senior researcher at the chair of computer architecture (Prof. Dr. A. Bode) at Technische Universität München (TUM). He received his Ph.D. from TUM in 2003 for research he did on load balancing issues in car crash simulation on industrial code (PamCrash, ESI) at BMW AG. Since then he is a research and teaching assistant at TUM, working on performance analysis tools using architecture simulation (KCachegrind) and corresponding cache optimization methods (e.g. DFG DiME project). Recent research involves accelerators and heterogeneous computing, corresponding tuning of data structures, as well as code generation techniques.

Research Interests

Parallel Computer architectures, High Performance Computing, Multi-/Manycore architectures, GPGPU, Performance analysis and optimization, Cache Simulation, Virtual Machines, Dynamic code generation.

I am interested in all kind of strategies towards improving efficiency of computations on various hardware structures, both on general purpose and specialized accelerator hardware (mostly towards HPC codes), including required tools (e.g. for performance analysis) and techniques on the SW/HW boundary (code generation, cache exploitation, ...). To this end, I regularly organize the UCHPC workshop (since 2010 with Euro-Par) about usage of "unconventional" hardware ideas for HPC computing. Further, being interested in performance analysis tools, I am co-organizer of PSTI since years and member of VI-HPS maintaining the Callgrind/KCachegrind tool suite.

Memberships: ACM, GI, Zuse-Gesellschaft

Teaching

For student works (bachelor/master thesis, IDP, guided research), see here. Or even better, please ask by mail for a meeting to discuss current open topics.

Summer Term 16

Winter Term 15/16

Summer Term 15

Winter Term 14/15

  • Lecture Virtualization Techniques
  • Seminar Programming models and code generation
  • Seminar Akzeleratorarchitekturen
  • Introduction to computer architecture: central exercise (microcode programming)

Supervised Student Work (recent)

  • A. Engelke: Using LLVM to Optimize Binary Re-Writing at Runtime, Guided Research (ongoing)
  • J. Rodrigues: Mutual Influence of Applications for Co-Scheduling, Guided Research (ongoing)
  • D.A. Suarez Trujillo: Design and Implementation of a Feature Detection Algorithm for Space Debris Detection on the High Performance Data Processor (HPDP), Master Thesis, Oct 2015
  • D.A. Ortiz-Yepes: Page Migration Strategies on NUMA Systems Based on Sampling, Master Thesis, Nov 2015
  • T. Geissler: A tool for efficient analysis of Memory Access Behaviour of HPC Applications, Bachelor Thesis, Mar 2015
  • S. Bartels: Investigation of the Portability of an Image Processing Algorithm on a Reconfigurable Space-borne Parallel Processor, Master Thesis, Aug 2014
  • L. Kowalczyk: Design and Implementation of an Automatic Tuning Solution for GPU Programs, Master Thesis, Mai 2014
  • I. Vadasz: Hardware Transactional Memory for Cache Simulation, Master Thesis, April 2014
  • G. Kukreja: Host compiled simulation to estimate time and power consumption of embedded systems, Master Thesis, Nov 2014
  • S. Hertle: Adaptive Usage of Hardware Transactional Memory on Haswell Processors, Bachelor Thesis, Oct. 2014
  • J. Kranz: Generating Fast Code Generators, Interdisciplinary Project, 2013
  • M. Plichta: Faster Sparse Matrix Operations by Code Generation Embedding Prefetching, Bachelor Thesis, Aug. 2013

Research

Projects

Talks (recent)

  • Cache Performance Analysis with Callgrind and KCachegrind. 21th VI-HPS Tuning Workshop, Garching, April 2016, Garching.
  • Co-Scheduling: Increasing Efficiency for HPC. Minisymposium "Middleware in the Era of Extreme Scale Computing", 17th SIAM PP, Paris, April 2016.
  • Detailed Characterization of HPC Applications for Co-Scheduling. 1st Workshop on Co-Scheduling of HPC Applications, HiPEAC 2016, Prague, Czech Republic, January 2016.
  • Dynamic code generation for HPC, ScalPerf'15, Bertinoro, Italy, September 2015
  • Analysis and Optimization of the Memory Access Behavior of Applications. Summer School "École Optimisation 2014", Université de Strasbourg, July 2014
  • Valgrind, Dynamic Binary Instrumentation and what you can do with it. Invited talk, EDF, Paris, March 2014
  • Effiziente System-Virtualisierung auf ARM-Archikturen. Eingeladener Vortrag im Rahmen der Vorlesung "Virtualisierte Systeme" (Vitalian Danciu), LMU, January 2014
  • Architecture Simulation for HPC Programmers. Invited talk, "RBP-Vortragsreihe", LRZ, Munich. November 2013.
  • Data Transfer Requirement Analysis with Bandwidth Curves. At 6th Workshop on Productivity and Performance, Euro-Par 2013. Aachen, Germany, August 2013.
  • Implicit and Task-Based Approaches to Heterogeneous Programming. Invited lecture (with hands-on sessions) at CEA-EDF-Inria Computer Science Summer School 2013 (Programming Heterogeneous Parallel Architectures). Cadarache, France, June/July 2013.
  • Message-passing and threads. Invited talk at ComplexHPC Spring School 2013 (EU COST Action IC0805). Uppsala, Sweden. June 2013.
  • Architecture Simulation for Performance Optimization. Invited talk, LMU, Munich. January 2013.

Co-Organized Scientific Events (recent)

    2016

    • December 2016, Granada, ES: First International Workshop on Data Locality in Modern Computing Systems (DLMCS 2016, with ICA3PP 2016)
    • August 2016, Grenoble, FR: 9th Workshop on UnConventional High Performance Computing 2016 (UCHPC 2016, with Euro-Par 2016)
    • August 2016, Philadephia, US: Sixth International Workshop on Parallel Software Tools and Tool Infrastructures (PSTI 2016)
    • January 2016, Prague, CZ: 1st Workshop on Co-Scheduling of HPC Applications 2016 (COSH 2016, with HiPEAC 2016)

    Older

    • August 2015, Vienna, AT: UCHPC 2015, Workshop at Euro-Par 2015
    • September 2014, Minneapolis, US: Fifth International Workshop on Parallel Software Tools and Tool Infrastructures (PSTI 2014)
    • August 2014, Porto, Portugal: 7th Workshop on UnConventional High Performance Computing 2014 (UCHPC 2014)
    • May 2014, Barcelona, ES: Thematic Session on Dynamic co-optimization of applications and resource management, HiPEAC Computer Systems Week.
    • October 2013, Lyon, France: Fourth International Workshop on Parallel Software Tools and Tool Infrastructures (PSTI 2013)
    • September 2013, Munich, Germany. PhD Forum at International Conference on Parallel Computing (ParCo2013)
    • August 2013, Aachen, Germany: 6th Workshop on UnConventional High Performance Computing 2013 (UCHPC'13)
    • May 2013, Ischia, Italy: Special Session on "Emerging Trends in Dataflow Computing" at the ACM International Conference on Computing Frontiers 2013 (see here).

Program Committee Memberships

    2016

    • ACM International Conference on Computing Frontiers 2016 (CF 2016)
    • IEEE International Parallel and Distributed Processing Symposium 2016 (IPDPS 2016)
    • International Conference on High Performance Computing and Simulation (HPCS 2016)
    • 2nd IEEE International Conference on Green High Performance Computing (ICGHPC16
    • 1st SYCL Programming Workshop (SYCL16, with PPoPP16)
    • 12th Workshop on Dependability and Fault Tolerance (VERFE16, with ARCS 2016)
    • 1st Workshop on Co-Scheduling of HPC Applications 2016 (COSH 2016, with HiPEAC 2016)
    • 1st Workshop on Performance and Scalability of Storage Systems 2016 (WOPSSS, with ISC 2016)
    • International Workshop on High Performance Platform Management 2016 (HPPM 2016)
    • Nineth Workshop on UnConventional High Performance Computing 2016 (UCHPC 2016, with Euro-Par 2016)
    • Sixth International Workshop on Parallel Software Tools and Tool Infrastructures (PSTI 2016)
    • International Workshop on Performance, Power and Energy-Efficiency Optimization in Heterogeneous Systems (PPEO 2016, with VECPAR16)
    • 4th Workshop on Runtime and Operating Systems for the Many-core (ROME16, with Euro-Par 2016)

    Older

    • CF15, IPDPS15, ISPDC15, HIPC15, E-MuCoCoS15, UCHPC15, ROME15
    • ISPDC14, PSTI 2014, UCHPC14, ROME 2014, VERFE14
    • CF13, PARCO13, UCHPC13
    • SC11, Facing the Multicore-Challange 2011, PROPER11, HipHac11

Other Organizational Roles

  • Steering Committee Member for Computing Frontiers Conference
  • Local Arrangements Chair, ICS 2014
  • Web Chair, Computing Frontiers 2014
  • Publication Chair, Computing Frontiers 2013
  • Special Session Char, Computing Frontiers 2012
  • Publication Chair, Computing Frontiers 2010
  • Workshop Chair, Computing Frontiers 2009

Publications

    2016

    • Josef Weidendorfer and Jens Breitbart. Detailed Characterization of HPC Applications for Co-Scheduling. In Proceedings of the first Workshop on Co-Scheduling of HPC Applications (COSH 2016). Prague, Czech Republic, 2016.
    • Josef Weidendorfer and Jens Breitbart. The Case for Binary Rewriting at Runtime for Efficient Implementation of High-Level Programming Models in HPC. In Proceedings of the 21st int. Workshop on High-Level Parallel Programming Models and Supportive Environments (HIPS 2016). Chicago, US, 2016.
    • Josef Weidendorfer and Jens Breitbart. Inclusive Cost Attribution for Cache Use Profiling. In Proceedings of the Workshop for Tools for Program Development and Analysis in Computational Science at ICCS 2016 (TOOLs 2016).. San Diego, US, 2016.
    • Jens Breitbart, Josef Weidendorfer, and Carsten Trinitis. Automatic Co-scheduling based on Main Memory Bandwidth Usage. In Proceedings of the 20th Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP 2016). Chicago, US, 2016.
    • Josef Weidendorfer. Simulation Driven Performance Analysis for Software Optimization. Habilitation Thesis. Technische Universität München, 2016.

    2015

    • Jens Breitbart, Josef Weidendorfer, and Carsten Trinitis. Case Study on Co-Scheduling for HPC Applications. In International Workshop on Scheduling and Resource Management for Parallel and Distributed Systems (SRMPDS 2015). Beijing, China, 2015.
    • Proceedings of UCHPC15. S. Hunold, A. Costan, D. Giménez, A. Iosup, L. Ricci, M.E. Gómez Requena, V. Scarano, A.L. Varbanescu, S.L. Scott, S. Lankes, J. Weidendorfer, and M. Alexander, editors, Euro-Par 2015: Parallel Processing Workshops, volume 9523 of Lecture Notes in Computer Science. Springer, 2015.

    2014

    • Minh Le, Max Walter, and Josef Weidendorfer. Improving the Kuo-Lu-Yeh algorithm for assessing Two-Terminal Reliability. 10th European Dependable Computing Conference (EDCC 2014). Newcastle, UK, 2014.
    • Minh Le, Josef Weidendorfer, and Max Walter. A Novel Variable Ordering Heuristic for BDD-Based k-Terminal Reliability. 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2014). Atlanta, US, 2014.
    • Proceedings of UCHPC13. Dieter an Mey, Michael Alexander, Paolo Bientinesi, Mario Cannataro, Carsten Clauss, Alexandru Costan, Gabor Kecskemeti, Christine Morin, Laura Ricci, Julio Sahuquillo, Martin Schulz, Vittorio Scarano, Stephen L. Scott, and Josef Weidendorfer, editors, Euro-Par 2013: Parallel Processing Workshops. BigDataCloud, DIHC, FedICI, HeteroPar, HiBB, LSDVE, MHPC, OMHI, PADABS, PROPER, Resilience, ROME, and UCHPC 2013. Aachen, Germany, August 26-27, 2013. Revised Selected Papers, volume 8374 of Lecture Notes in Computer Science. Springer, 2014.

    2013

    • David Büttner, Jean-Thomas Aquaviva, and Josef Weidendorfer. Real Asynchronous MPI Communication in Hybrid Codes through OpenMP Communication Tasks. 19th IEEE International Conference on Parallel and Distributed Systems. Seoul, Korea, 2013.
    • Josef Weidendorfer. Data Transfer Requirement Analysis with Bandwidth Curves. 6th Workshop on Productivity and Performance. EuroPar 2013 Workshops, Aachen, Germany. 2013.
    • Thomas Müller, Josef Weidendorfer, and Andreas Blaszczyk: Expression Tree Evaluation by Dynamic Code Generation - Are Accelerators up for the Task? In Proceedings of ICPP 2013. Lyon, France. 2013.
    • Euro-Par 2012: Parallel Processing Workshops. BDMC, CGWS, HeteroPar, HiBB, OMHI, Paraphrase, PROPER, Resilience, UCHPC, VHPC, Rhodes Islands, Greece, August 27-31, 2012. Revised Selected Papers. Ioannis Caragiannis, Michael Alexander, Rosa Maria Badia, Mario Cannataro, Alexandru Costan, Marco Danelutto, Frédéric Desprez, Bettina Krammer, Julio Sahuquillo, Stephen L. Scott, and Josef Weidendorfer, editors, Euro-Par Workshops, volume 7640 of Lecture Notes in Computer Science. Springer, 2013.

    2012

    • Alin F. Murarasu, Gerrit Buse, Dirk Pflüger, Josef Weidendorfer, and Arndt Bode. fastsg: A Fast Routines Library for Sparse Grids. In Proceedings of the International Conference on Computational Science (ICCS 2012), volume 9 of Procedia CS, pages 354-363, 2012.
    • A. F. Murarasu and J. Weidendorfer. Building Input Adaptive Parallel Applications: A Case Study of Sparse Grid Interpolation. In Proceedings of the 15th IEEE International Conference on Computational Science and Engineering (ICCSE), 2012.
    • Michael Gerndt, Frank Hannig, Andreas Herkersdorf, Andreas Hollmann, Marcel Meyer, Sascha Roloff, Josef Weidendorfer, Thomas Wild, and Aurang Zaib. An integrated Simulation Framework for Invasive Computing. In Forum on specification and Design Languages (FDL 2012), pages 209-216, 2012.
    • Michael Gerndt, Andreas Hollmann, Marcel Meyer, Martin Schreiber, and Josef Weidendorfer. Invasive computing with iOMP. In Forum on specification and Design Languages (FDL 2012), pages 225-231, 2012.
    • Euro-Par 2011: Parallel Processing Workshops - CCPI, CGWS, HeteroPar, HiBB, HPCVirt, HPPC, HPSS, MDGS, ProPer, Resilience, UCHPC, VHPC, Bordeaux, France, August 29 - September 2, 2011, Revised Selected Papers. Michael Alexander, Pasqua D'Ambra, Adam Belloum, George Bosilca, Mario Cannataro, Marco Danelutto, Beniamino Di Martino, Michael Gerndt, Emmanuel Jeannot, Raymond Namyst, Jean Roman, Stephen L. Scott, Jesper Larsson Träff, Geoffroy Vallée, and Josef Weidendorfer, editors, Euro-Par Workshops, volume 7155 of Lecture Notes in Computer Science. Springer, 2012.
    • Minh Lê, Max Walter, and Josef Weidendorfer. A Memory-efficient Bounding Algorithm for the Two-terminal Reliability Problem. In Second Workshop on Quantitative Models for Performance and Dependability (QMPD 2012), volume 291 of Electronic Notes in Theoretical Computer Science, pages 15-25. Elsevier, 2012.

    2011

    • Alin Murarasu, Josef Weidendorfer, and Arndt Bode. Workload Balancing on Heterogeneous Systems: A Case Study of Sparse Grid Interpolation. In Proceedings of UCHPC 2011. To appear in EuroPar-2011 Workshop Proceedings. Springer, 2011.
    • Michael Bader, Hans-Joachim Bungartz, Michael Gerndt, Andreas Hollmann, and Josef Weidendorfer. Invasive Programming as a Concept for HPC. In Proceedings of the 10h IASTED International Conference on Parallel and Distributed Computing and Networks 2011 (PDCN 2011). Innsbruck, Austria, 2011.
    • Alin Murarasu, Josef Weidendorfer, Gerrit Buse, Daniel Butnaru, and Dirk Pflüeger. Compact Data Structure and Scalable Algorithms for the Sparse Grid Technique. In Proceedings of the 16th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP'11), February 2011.
    • Josef Weidendorfer, Tilman Küstner, and Sally A. McKee. Performance Optimization by Dynamic Code Transformation. In Proceedings of Computing Frontiers 2011. ACM Press, 2011. Extended Abstract.
    • Josef Weidendorfer. Intel Core Microarchitecture, x86 Processor Family. In David Padua, editor, Encyclopedia of Parallel Computing. Springer, 2011.

    2010

    • Alexander Heinecke, Carsten Trinitis, and Josef Weidendorfer. Porting existing cache-oblivious Linear Algebra HPC Modules to Larrabee Architecture. In Proceedings of Computing Frontiers 2010. ACM Press, May 2010.
    • Hans Hacker, Carsten Trinitis, Josef Weidendorfer, and Matthias Brehm. Considering GPGPU for HPC Centers: Is it Worth the Effort?. In Proceedings of Conference for Young Scientists: Facing the Multicore-Challenge. Heidelberg, 2010.
    • Carsten Trinitis, Tilman Küstner, Josef Weidendorfer, and J. Smajic. Sparse Matrix Operations on Multi-Core Architectures. Journal of Supercomputing (selected papers of PaCT-2009), DOI 10.1007/s11227-010-0428-9. Springer, 2010.
    • Tilman Küstner, Peter Pedron, Jasmine Schirmer, Melanie Hohberg, Josef Weidendorfer, and Sibylle I. Ziegler. Fast System Matrix Generation Using the Detector Response Function Model on Nvidia Fermi GPUs. In Proceedings of IEEE Medical Imaging Conference 2010. IEEE, 2010. Extended Abstract.

    2009

    • Tilman Küstner, Josef Weidendorfer, and Tobias Weinzierl. Argument Controlled Profiling. In Proceedings of 2nd Workshop on Productivity and Performance (PROPER 2009). Springer, 2009.
    • Tilman Küstner, Josef Weidendorfer, Jasmin Schirmer, T. Klug, C. Trinitis, and S. Ziegler. Parallel MLEM on Multicore Architectures. In Proceedings of 9th International Conference on Computational Science (ICCS 2009), number 5544 of LNCS, pages 491-500. Springer, 2009.
    • Michael Bader and Josef Weidendorfer. Exploiting Memory Hierarchies in Scientific Computing. Extended Abstract. In Proceedings of the 2009 International Conference on High Performance Computing and Simulation (HPCS2009). IEEE. Leipzig, Germany, 2009.
    • Carsten Trinitis, Tilman Küstner, Josef Weidendorfer, and J. Smajic. Sparse Matrix Operations on Multi-Core Architectures. In Proceedings of 11th International Conference on Parallel Computing Technologies (PaCT 2009). Springer, 2009.
    • Stephan M. Günther and Josef Weidendorfer. Assessing cache false sharing effects by dynamic binary instrumentation. In WBIA '09: Proceedings of the Workshop on Binary Instrumentation and Applications, pages 26-33. ACM Press. New York, 2009.

    2008

    • Tobias Klug, Michael Ott, Josef Weidendorfer, and Carsten Trinitis. Autopin – Automated Optimization of Thread-to-Core Pinning on Multicore Systems. Transactions on High-Performance Embedded Architectures and Compilers (Transactions on HiPEAC), volume 3 (4), pages 219-235, 2008.
    • Josef Weidendorfer and Carsten Trinitis. Off-loading application controlled data prefetching in numerical codes for multicore processors. International Journal of Computational Science and Engineering (IJCSE), volume 4 (1), pages 22-28, 2008.
    • Josef Weidendorfer. Tools for high performance computing: Proceedings of the 2nd International Workshop on Parallel Tools for High Performance Computing, chapter Sequential Performance Analysis with Callgrind and KCachegrind. Springer. Stuttgart, Juli 2008.
    • Michael Ott, Tobias Klug, Josef Weidendorfer, and Carsten Trinitis. autopin - Automated Optimization of Thread-to-Core Pinning on Multicore Systems. Proceedings of 1st Workshop on Programmability Issues for Multi-Core Computers (MULTIPROG), 2008.
    • Julian Seward, Nick Nethercode, and Josef Weidendorfer. Valgrind 3.3. Advanced Debugging and Profiling for GNU/Linux applications. Network Theory Limited. UK, March 2008.

    2007

    • Josef Weidendorfer, Michael Ott, Tobias Klug, and Carsten Trinitis. Latencies of Conflicting Writes on Contemporary Multi-core Architectures. In Ninth International Conference on Parallel Computing Technologies (PaCT-2007), number 4671 of LNCS, pages 318-327. Springer. Pereslavl-Zalessky, Russia, 2007.
    • Josef Minde, Josef Weidendorfer, Tobias Klug, and Carsten Trinits. PET-Bildrekonstruktion auf der Cell-BE. In Tagungsband Kommunikation in Clusterrrechnern und Clusterverbundsystemen, 3. Tagung. RWTH Aachen. Aachen, Germany, December 2007.
    • Josef Weidendorfer, Michael Ott, Tobias Klug, and Carsten Trinitis. False Sharing auf aktuellen Mikroprozessoren. In Tagungsband 2. Workshop "Kommunikation in Clusterrechnern und Clusterverbundsystemen" (KiCC), volume ISSN 0947-5125. Chemnitz, Deutschland, February 2007.
    • Josef Weidendorfer. Understanding Memory Access Bottlenecks on Multi-core. In Book of Abstracts of the International Conference ParCo 2007, volume 37 of NIC Series. Forschungszentrum Jülich, 2007.

    2006

    • Josef Weidendorfer and Carsten Trinitis. Block Prefetching for Numerical Codes. In Proceedings of 19th Symposium on Simulation Techniques (ASIM 2006). Hannover, Germany, September 2006.
    • Carsten Trinits, Tobias Klug, Max Walter, and Josef Weidendorfer. Automatic High Voltage Apparatus Optimization. Dresden, Germany, June 2006.
    • Josef Weidendorfer and Carsten Trinitis. Cache Optimizations for Iterative Numerical Codes Aware of Hardware Prefetching. In Applied Parallel Computing, State of the Art in Scientific Computing, 7th International Workshop, PARA 2004, Lyngby, Denmark, June 20-23, 2004, Revised Selected Papers, volume 3732 of LNCS, pages 921-927. Springer, 2006. (Slides)

    2005

    • Josef Weidendorfer and Carsten Trinitis. Collecting and Exploiting Cache-Reuse Metrics. In ICCS 2005: 5th International Conference on Computational Science, volume 3515 of LNCS, pages 191-198. Springer, May 2005. (Slides)
    • Jie Tao, Jürgen Jeitner, Carsten Trinitis, Wolfgang Karl, and Josef Weidendorfer. Comprehensive Cache Inspection with Hardware Monitors. In Proceedings of 9th International Conference on Parallel Computing Technologies (PaCT 2005), number 3606 of LNCS, pages 331-345. Springer, 2005.

    2004

    2003

    • Josef Weidendorfer. Konzepte zur Optimierung der Skalierbarkeit von parallelen Fahrzeugkollisionsberechnungen und ihre industrielle Realisierbarkeit. Dissertation. Volume 29 of Research Report Series, Lehrstuhl für Rechnertechnik und Rechnerorganisation, Technische Universität München. Shaker Publishing, 2003.

    2001

    • Josef Weidendorfer and Peter Luksch. A Framework for Transparent Load Balancing in Parallel Numerical Simulation. In Proceedings of the 34th annual symposium on Simulation, pages 125-132. IEEE Computer Society. Washington, DC, USA, 2001.

    1999

    • Hermann Hellwagner and Josef Weidendorfer. SCI Sockets Library. In SCI: Scalable Coherent Interface, Architecture and Software for High-Performance Compute Clusters, volume 1734 of LNCS, pages 209-229. Springer. London, UK, 1999.
    • Josef Weidendorfer. Load balancing Contact 36 in PAMCRASH MPP. In Proceedings of EURO-PAM’99. Darmstadt, Germany, 1999.

    1998

    • Michael Eberl, Hermann Hellwagner, Wolfgang Karl, Markus Leberecht, and Josef Weidendorfer. Fast Communication Libraries on a SCI Cluster. In Hermann Hellwagner and Alexander Reinefeld, editors, Scalable Coherent Interface: Technology and Applications. Proceedings of SCI Europe'98, pages 165-175. Cheshire Henbury Tamwoth House, P.O. Box 103 Macclesfield SK11 8UW, UK, 1998.

    1997

    • Josef Weidendorfer. Entwurf und Implementierung einer Socket-Bibliothek für ein SCI-Netzwerk. Diploma thesis. Institut für Informatik, Technische Universität München. February 1997.