Seminar Programming Models and Code Generation WS16/17
This seminar will be held in English.
June 30, 2016, 13:45 in room 01.06.020
Registration is done via central assignment (as with all other seminars).
This is an external seminar. Part of expenses can be covered by TUM, but part also needs to be covered by the students (around 50 Euro). As we have to book early, if you get assigned to this seminar, we will ask you for a deposit of 30,- Euro in advance. This will be used for the expenses for the trip to Frauenchiemsee. You may cancel your registration before October, and get the money back (otherwise refunding is not possible).
- Module Catalogue: IN4590 , IN2107
- Time and Location: This course will be offered as a block seminar at Kloster Frauenwörth at Chiemsee. Confirmed date is Thursday/Friday January 19/20, 2017. You will get an email with more details in beginning of January.
|Heap bounds protection with low fat pointers||A.F.E.||Michael Petter|
|User-level Access to Privileged CPU Features||A.G.H.||Josef Weidendorfer|
|OpenMP 4.0's Effectiveness as Heterogeneous Parallel Programming Model||A.K.||Josef Weidendorfer|
|Thread-level speculation with kernel support||K.K.||Michael Petter|
|High-level Description of Parallel Graph Algorithms||B.M.||Michael Gerndt|
|Intel Control-flow Enforcement Technology targetting ROP||J.P.||Josef Weidendorfer|
|Block-free concurrent GC: stack scanning and copying||L.P.P.V.||Michael Petter|
|SafeStack: Code-Pointer Integrity||E.P.||Josef Weidendorfer|
|A lightweight in-place implementation for software thread-level speculation||F.R.||Michael Petter|
|Remix: online detection and repair of cache contention for the JVM||R.S.||Michael Petter|
|Thread-Level Speculation using Hardware Transactional Memory||L.S.||Michael Petter|
|OpenACC to FPGA: Directive-Based High-Performance Reconfigurable Computing||A.W.||Josef Weidendorfer|
For literature on your topic, discuss with your supervisor.
- Deadline for paper draft: December 5, 2016
- Peer Review: until December 12, 2016
- Final Paper Due: January 16, 2017
- Block Seminar: Thursday/Friday January 19/20, 2017 (more details to come)
The seminar is organized similar to a scientific conference. All talks will be presented 'en bloc' within two consecutive days. The conference will take place on the island "Frauenchiemsee".
In order to qualify for the ECTS credits, participants have to prepare a paper and present a talk. The paper should have a length of between 8 and 10 pages using the latex template available below. The paper is subject to a review process among students: every attendee will have to review two other papers. The talk should be 25 minutes long. It strictly must not be longer than 30 minutes in any case.
The final grade is influenced mostly by paper/talk quality (half/half), but also the timeliness and quality of reviews will be taken into account. Delivering either the paper or the talk in unacceptable quality will result in total failure.
In this seminar we discuss novel programming models and code generation techniques with a focus on modern processor architectures like multiprocessors, graphic accelerators, high performance computers.
Topics (more at the preliminary meeting):
- Code Integrity
- Control-flow Enforcement Technology: new Intel ISA extension targeting ROP (Assigned)
- Heap bounds protection with low fat pointers (Assigned)
- SafeStack: Code-Pointer Integrity (Assigned)
- User-level Access to Privileged CPU Features (Assigned)
- Automatic Parallelization
- A lightweight in-place implementation for software thread-level speculation (Assigned)
- Thread-level speculation with kernel support (Assigned)
- Speculative Decoupled Software Pipelining
- Thread-Level Speculation using Hardware Transactional Memory (Assigned)
- Parallel Programming Models
- High-level Description of Parallel Graph Algorithms (Assigned)
- Programmable vs. Domain-specific Accelerators
- OpenACC to FPGA: A Framework for Directive-Based High-Performance Reconfigurable Computing (Assigned)
- Hierarchical Parallel Dynamic Dependence Analysis for Recursively Task-Parallel Programs
- OpenMP 4.0's Effectiveness as a Heterogeneous Parallel Programming Model (Assigned)
- Iceberg: a tool for static analysis of Java critical sections
- Block-free concurrent GC: stack scanning and copying (Assigned)
- Remix: online detection and repair of cache contention for the JVM (Assigned)
- Memory Scalability Analyzation